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Isolated Sigma-Delta Modulator AD7400
FEATURES
10 MHz clock rate Second-order modulator 16 bits no missing codes 2 LSB INL typical at 16 bits 3.5 V/C maximum offset drift On-board digital isolator On-board reference Low power operation: 18 mA maximum at 5.25 V -40C to +105C operating range 16-lead SOIC package AD7401, external clock version Safety and regulatory approvals UL recognition 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 891 V peak
GENERAL DESCRIPTION
The AD7400 1 is a second-order, - modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc. iCoupler(R) technology. The AD7400 operates from a 5 V power supply and accepts a differential input signal of 200 mV (320 mV full scale). The analog input is continuously sampled by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). The serial interface is digitally isolated. High speed CMOS, combined with monolithic air core transformer technology, means the on-chip isolation provides outstanding performance characteristics superior to alternatives such as optocoupler devices. The part contains an on-chip reference. The AD7400 is offered in a 16-lead SOIC and has an operating temperature range of -40C to +105C.
APPLICATIONS
AC motor controls Data acquisition systems A/D + opto-isolator replacements
VDD1
1
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
FUNCTIONAL BLOCK DIAGRAM
VDD2
AD7400
VIN+ VIN-
T/H
- ADC UPDATE WATCHDOG
BUF
ENCODE
DECODE
MDAT
REF
CONTROL LOGIC
UPDATE
WATCHDOG
ENCODE
DECODE
MCLKOUT
GND1
GND2
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
04718-001
AD7400 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 4 Insulation and Safety-Related Specifications............................ 5 Regulatory Information............................................................... 5 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics .............................................................................. 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ..............................................9 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 Circuit Information.................................................................... 13 Analog Input ............................................................................... 13 Differential Inputs ...................................................................... 14 Digital Filter ................................................................................ 14 Application Information................................................................ 17 Grounding and Layout .............................................................. 17 Evaluating the AD7400 Performance ...................................... 17 Insulation Lifetime ..................................................................... 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
12/06--Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Table 6............................................................................ 7 Changes to Analog Input Section................................................. 13 Changes to Figure 26...................................................................... 15 1/06--Revision 0: Initial Version
Rev. A | Page 2 of 20
AD7400 SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, VIN+ = -200 mV to +200 mV, and VIN- = 0 V (single-ended); TA = TMIN to TMAX, fMCLK = 10 MHz, tested with Sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. 1 Table 1.
Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity 3 Differential Nonlinearity3 Offset Error3 Offset Drift vs. Temperature3 Offset Drift vs. VDD1 Gain Error3 Gain Error Drift vs. Temperature3 Gain Error Drift vs. VDD13 ANALOG INPUT Input Voltage Range Dynamic Input Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-(Noise + Distortion) Ratio (SINAD)3 Y Version1, 2 16 15 25 0.9 0.5 50 3.5 1 120 1 23 110 200 7 0.5 10 70 65 79 71 -88 -88 11.5 25 30 VDD2 - 0.1 0.4 4.5/5.25 3/5.5 12 6 4 Unit Bits min LSB max LSB max LSB max mV max V typ V/C max V/C typ V/V typ mV max V/C typ V/V typ mV min/mV max A max A typ pF typ dB min dB min dB typ dB min dB typ dB typ Bits kV/s min kV/s typ V min V max V min/V max V min/V max mA max mA max mA max Test Conditions/Comments Filter output truncated to 16 bits -40C to +85C; 2 LSB typical >85C to 105C Guaranteed no missing codes to 16 bits TA = 25C -40C to +105C
-40C to +105C
For specified performance; full range 320 mV VIN+ = 400 mV, VIN- = 0 V VIN+ = VIN- = 0 V VIN+ = 35 Hz, 400 mV p-p sine -40C to +85C >85C to 105C -40C to +105C
Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Effective Number of Bits (ENOB)3 Isolation Transient Immunity3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL POWER REQUIREMENTS VDD1 VDD2 IDD1 4 IDD2 5
IO = -200 A IO = +200 A
VDD1 = 5.25 V VDD2 = 5.5 V VDD2 = 3.3 V
1 2 3
Temperature range is -40C to +85C. All voltages are relative to their respective ground. See the Terminology section. 4 See Figure 14. 5 See Figure 15.
Rev. A | Page 3 of 20
AD7400
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.25 V, VDD2 = 3 V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted. 1 Table 2.
Parameter fMCLKOUT 2 t1 3 t23 t3 t4
1 2
Limit at TMIN, TMAX 10 9/11 40 10 0.4 x tMCLKOUT 0.4 x tMCLKOUT
Unit MHz typ MHz min/MHz max ns max ns min ns min ns min
Description Master clock output frequency Master clock output frequency Data access time after MCLK rising edge Data hold time after MCLK rising edge Master clock low time Master clock high time
Sample tested during initial release to ensure compliance. Mark space ratio for clock output is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
200A
IOL
TO OUTPUT PIN
+1.6V CL 25pF 200A IOH
04718-002
Figure 2. Load Circuit for Digital Output Timing Specifications
t4
MCLKOUT
04718-003
t1
MDAT
t2
t3
Figure 3. Data Timing
Rev. A | Page 4 of 20
AD7400
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 3.
Parameter Input-to-Output Withstand Momentary Withstand Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol VISO L(I01) L(I02) Value 3750 min 7.46 min 8.1 min 0.017 min >175 IIIa Unit V mm mm mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material group (DIN VDE 0110, 1/89, Table 1)
CTI
REGULATORY INFORMATION
Table 4.
UL 1 Recognized Under 1577 Component Recognition Program1 3750 V rms Isolation Voltage CSA Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 630 V rm maximum working voltage File 205078 VDE 2 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012 Basic insulation, 891 V peak Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 Reinforced insulation, 891 V peak File 2471900-4880-0001
File E214100
1 2
In accordance with UL 1577, each AD7400 is proof tested by applying an insulation test voltage 4500 V rms for 1 second (current leakage detection limit = 7.5 A). In accordance with DIN EN 60747-5-2, each AD7400 is proof tested by applying an insulation test voltage 1671 V peak for 1 second (partial discharge detection limit = 5 pC).
Rev. A | Page 5 of 20
AD7400
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 5.
Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage 300 V rms For Rated Mains Voltage 450 V rms For Rated Mains Voltage 600 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, Table 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT-TO-OUTPUT TEST VOLTAGE, METHOD B1 VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC INPUT-TO-OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/3 VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 sec) SAFETY-LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, ALSO SEE Figure 4) Case Temperature Side 1 Current Side 2 Current INSULATION RESISTANCE AT TS, VIO = 500 V
350 300
Symbol
Characteristic I-IV I-II I-II 40/105/21 2 891 1671 1426 1069
Unit
VIORM VPR VPR
V peak V peak V peak V peak V peak C mA mA
VTR TS IS1 IS2 RS
6000 150 265 335 >109
SAFETY-LIMITING CURRENT (mA)
250 SIDE #2 200 150 SIDE #1 100 50 0
0
50
100 150 CASE TEMPERATURE (C)
200
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN 60747-5-2
Rev. A | Page 6 of 20
04718-026
AD7400 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 6.
Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Output Voltage to GND2 Input Current to Any Pin Except Supplies 1 Operating Temperature Range Storage Temperature Range Junction Temperature SOIC Package JA Thermal Impedance JC Thermal Impedance Resistance (Input-to-Output), RI-O Capacitance (Input-to-Output), CI-O 3 Pb-Free Temperature, Soldering Reflow ESD
1 2
Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to VDD1 + 0.3 V -0.3 V to VDD2 + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 113C (UL) 2 89.2C/W 55.6C/W 1012 1.7 pF typ 260 (+0)C 1.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Maximum Continuous Working Voltage1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage
1
Max 565 891 891
Unit VPK VPK V
Constraint 50-year minimum lifetime Maximum CSA/VDE approved working voltage Maximum CSA/VDE approved working voltage
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
Transient currents of up to 100 mA do not cause SCR to latch up. UL certification applies up to 113C only. 3 f = 1 MHz.
Rev. A | Page 7 of 20
AD7400 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1 VIN+ 2 VIN- 3 NC 5 NC 6 VDD1 7 GND1 8
16 GND2
AD7400
15 NC
TOP VIEW 14 VDD2 (Not to Scale) 13 MCLKOUT NC 4
12 NC 11 MDAT 10 NC 9
GND2
NC = NO CONNECT
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. 1, 7 2 3 4 to 6, 10, 12, 15 8 9, 16 11 Mnemonic VDD1 VIN+ VIN- NC GND1 GND2 MDAT Description Supply Voltage, 4.5 V to 5.25 V. This is the supply voltage for the isolated side of the AD7400 and is relative to GND1. Positive Analog Input. Specified range of 200 mV. Negative Analog Input. Normally connected to GND1. No Connect. Ground 1. This is the ground reference point for all circuitry on the isolated side. Ground 2. This is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKOUT output and valid on the following MCLKOUT rising edge. Master Clock Logic Output. 10 MHz typical. The bit stream from the modulator is valid on the rising edge of MCLKOUT. Supply Voltage. 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
13 14
MCLKOUT VDD2
Rev. A | Page 8 of 20
04718-004
AD7400 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, using 20 kHz brickwall filter, unless otherwise noted.
100 90 80 70
SINAD (dB)
-90
200mV p-p SINEWAVE ON VDD1 NO DECOUPLING VDD1 = VDD2 = 4.5V TO 5.25V
-80 -70 -60 -50 -40 -30 -20
VDD1 = VDD2 = 5V
PSRR (dB)
60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 800 900
04718-005
1000
0 0.195
0.215
0.235
0.255
0.275
0.295
0.315
SUPPLY RIPPLE FREQUENCY (kHz)
INPUT AMPLITUDE (V)
Figure 6. PSRR vs. Supply Ripple Frequency Without Supply Decoupling (1 MHz Filter Used)
-90 -80 -70 -60 0.5 0.4 0.3
Figure 9. SINAD vs. VIN
VIN+ = -200mV TO +200mV VIN- = 0V
DNL ERROR (LSB)
VDD1 = VDD2 = 4.5V
0.2 0.1 0 -0.1 -0.2
SINAD (dB)
-50 -40 VDD1 = VDD2 = 5.25V -30 -20
04718-006
VDD1 = VDD2 = 5V
0
-0.4
0
500
1000
1500
2000
2500
3000
3500
4000
0
10000
20000
30000 CODE
40000
50000
60000
INPUT FREQUENCY (Hz)
Figure 7. SINAD vs. Analog Input Frequency for Various Supply Voltages
0 -20 -40 -60 -80
dB
0.8
Figure 10. Typical DNL, 200 mV Range (Using Sinc3 Filter, 256 Decimation Rate)
VIN+ = -200mV TO +200mV VIN- = 0V
8192 POINT FFT fIN = 35Hz SINAD = 79.6991dB THD = -92.6722dB DECIMATION BY 256 INL ERROR (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6
-100 -120 -140
04718-007
-180
0
2
4
6
8 10 12 14 FREQUENCY (kHz)
16
18
20
0
10000
20000
30000 CODE
40000
50000
60000
Figure 8. Typical FFT, 200 mV Range (Using Sinc3 Filter, 256 Decimation Rate)
Figure 11. Typical INL, 200 mV Range (Using Sinc3 Filter, 256 Decimation Rate)
Rev. A | Page 9 of 20
04718-010
-160
04718-009
-10
-0.3
04718-008
-10
AD7400
100 VDD1 = VDD2 = 4.5V
0.0036
IDD2 @ +25C
0.0035
VDD1 = VDD2 = 5V
50
IDD2 @ +85C
0
0.0034
OFFSET (V)
-50
IDD2 (A)
VDD1 = VDD2 = 5V
0.0033
IDD2 @ -40C
-100 VDD1 = VDD2 = 5.25V
04718-011
0.0032
-150
0.0031
04718-014
0.02
0.06
0.10
0.14
0.18
0.22
0.26
0.30
-0.34
-0.30
-0.26
-0.22
-0.18
-0.14
-0.10
-0.06
TEMPERATURE (C)
VIN DC INPUT VOLTAGE (V)
Figure 12. Offset Drift vs. Temperature for Various Supply Voltages
0.20 0.15 0.10 0.05
GAIN (%)
Figure 15. IDD2 vs. VIN at Various Temperatures
9 VDD1 = VDD2 = 4.5V TO 5.25V 6
VDD1 = VDD2 = 4.5V
IIN (A)
3
VDD1 = VDD2 = 5V
0 -0.05 -0.10
04718-012
0
-3
0.05
0.10
0.15
0.20
0.25
0.30
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
TEMPERATURE (C)
VIN+ DC INPUT (V)
Figure 13 . Gain Error Drift vs. Temperature for Various Supply Voltages
0.0099 0.0098 0.0097 0.0096 0.0095 TA = +85C VDD1 = VDD2 = 5V
0 -10
Figure 16. IIN vs. VIN+ DC Input
TA = +25C
-20 -30
IDD1 (A)
0.0094 0.0093 0.0092 0.0091 0.0090 0.0089
04718-013
TA = -40C
CMRR (dB)
-40 -50 -60 -70 -80 -90 -100 0.1 1 10 100 1000
04718-016
0.02
0.06
0.10
0.14
0.18
0.22
0.26
0.30
-0.34
-0.30
-0.26
-0.22
-0.18
-0.14
-0.10
-0.06
-0.02
0.34
-0.05
10000
VIN DC INPUT VOLTAGE (V)
RIPPLE FREQUENCY (kHz)
Figure 14. IDD1 vs. VIN at Various Temperatures
Figure 17. CMRR vs. Common-Mode Ripple Frequency
Rev. A | Page 10 of 20
0.35
-0.20 -45 -35 -25 -15 -5
5
15 25 35 45 55 65 75 85 95 105
-9
0
04718-015
-0.15
VDD1 = VDD2 = 5.25V
-6
-0.02
0.34
-200 -45 -35 -25 -15 -5
5 15 25 35 45 55 65 75 85 95 105
0.0030
AD7400
1.0 BANDWIDTH = 100kHz 0.8
11.0 10.8 10.6 10.4 VDD1 = VDD2 = 4.5V
NOISE (mV)
0.6
MCLKOUT (MHz)
10.2 10.0 9.8 9.6 VDD1 = VDD2 = 5.25V VDD1 = VDD2 = 5V
04718-024
0.4
0.2
04718-017
9.4 9.2
0
0.05
0.10
0.15
0.20
0.25
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.30
0
-5
5
15
25
35
45
55
65
75
85
-45
-35
-25
-15
95
TEMPERATURE (C)
VIN DC INPUT (V)
Figure 18. RMS Noise Voltage vs. VIN DC Input
Figure 19. MCLKOUT vs. Temperature for Various Supplies
Rev. A | Page 11 of 20
105
9.0
AD7400 TERMINOLOGY
Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, -200 mV (VIN+ - VIN-), Code 12,288 for the 16-bit level, and specified positive full scale, +200 mV (VIN+ - VIN-), Code 53,248 for the 16-bit level. Offset Error Offset is the deviation of the midscale code (Code 32,768 for the 16-bit level) from the ideal VIN+ - VIN- (that is, 0 V). Gain Error This includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (53,248 for the 16-bit level) from the ideal VIN+ - VIN- (+200 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (12,288 for the 16-bit level) from the ideal VIN+ - VIN- (-200 mV) after the offset error is adjusted out. Gain error includes reference error. Signal-to-(Noise + Distortion) Ratio (SINAD) This ratio is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Therefore, for a 12-bit converter, this is 74 dB. Effective Number of Bits (ENOB) The ENOB is defined by ENOB = (SINAD - 1.76)/6.02 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7400, it is defined as
THD(dB) = 20 log
where:
V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1
V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at 200 mV frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN- of frequency fS as CMRR (dB) = 10log(Pf/PfS) where: Pf is the power at frequency f in the ADC output. PfS is the power at frequency fS in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not converter linearity. PSRR is the maximum change in the specified full-scale (200 mV) transition point due to a change in power supply voltage from the nominal value (see Figure 6). Isolation Transient Immunity The isolation transient immunity specifies the rate of rise/fall of a transient pulse applied across the isolation boundary beyond which clock or data is corrupted. (It was tested using a transient pulse frequency of 100 kHz.)
Rev. A | Page 12 of 20
AD7400 THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7400 isolated - modulator converts an analog input signal into a high speed (10 MHz typ), single-bit data stream; the time average of the modulator's single-bit data is directly proportional to the input signal. Figure 22 shows a typical application circuit where the AD7400 is used to provide isolation between the analog input, a current sensing resistor, and the digital output, which is then processed by a digital filter to provide an N-bit word. A differential input of 320 mV results in a stream of ideally all ones. This is the absolute full-scale range of the AD7400, while 200 mV is the specified full-scale range, as shown in Table 9. Table 9. Analog Input Range
Analog Input Full-Scale Range Positive Full Scale Positive Specified Input Range Zero Negative Specified Input Range Negative Full Scale Voltage Input +640 mV +320 mV +200 mV 0 mV -200 mV -320 mV
ANALOG INPUT
The differential analog input of the AD7400 is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a 1-bit output stream. The sample clock (MCLKOUT) provides the clock signal for the conversion process as well as the output data-framing clock. This clock source is internal on the AD7400. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 20).
MODULATOR OUTPUT +FS ANALOG INPUT
To reconstruct the original information, this output needs to be digitally filtered and decimated. A Sinc3 filter is recommended because this is one order higher than that of the AD7400 modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 39 kHz, assuming a 10 MHz internal clock frequency. Figure 21 shows the transfer function of the AD7400 relative to the 16-bit output.
65535
53248
ANALOG INPUT
04718-019
-FS ANALOG INPUT
ADC CODE
SPECIFIED RANGE
Figure 20. Analog Input vs. Modulator Output
12288
A differential signal of 0 V results (ideally) in a stream of ones and zeros at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 200 mV produces a stream of ones and zeros that are high 81.25% of the time. A differential input of -200 mV produces a stream of ones and zeros that are high 18.75% of the time.
-320mV
-200mV ANALOG INPUT
+200mV +320mV
Figure 21. Filtered and Decimated 16-Bit Transfer Characteristic
ISOLATED 5V VDD1
NONISOLATED 5V/3V
AD7400
- MOD/ ENCODER
VDD2
VDD
SINC3 FILTER
DECODER MDAT MCLKOUT MDAT
CS SCLK
+ INPUT CURRENT RSHUNT
VIN+ VIN-
MCLK SDAT
DECODER GND1
ENCODER GND2 GND
04718-018
Figure 22. Typical Application Circuit
Rev. A | Page 13 of 20
04718-020
0
AD7400
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 23. A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half MCLKOUT cycle and settle to the required accuracy within the next half cycle.
A VIN+ 1k B 2pF 2pF
DIGITAL FILTER
A Sinc3 filter is recommended for use with the AD7400. This filter can be implemented on an FPGA or a DSP. The following Verilog code provides an example of a Sinc3 filter implementation on a Xilinx(R) Spartan-II 2.5 V FPGA. This code can possibly be compiled for another FPGA, such as an Altera(R) device. Note that the data is read on the negative clock edge in this case; although, it can be read on the positive edge, if preferred. Figure 28 shows the effect of using different decimation rates with various filter types.
/*Data is read on negative clk edge*/ module DEC256SINC24B(mdata1, mclk1, reset, DATA); input mclk1; input reset; input mdata1; filtered*/ output [15:0] DATA; integer location; integer info_file; reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [23:0] reg [15:0] reg [7:0] reg word_clk; reg init; ip_data1; acc1; acc2; acc3; acc3_d1; acc3_d2; diff1; diff2; diff3; diff1_d; diff2_d; DATA; word_count; /*used to clk filter*/ /*used to reset filter*/ /*ip data to be /*filtered op*/
A VIN- 1k B
MCLKOUT
A B A B
Figure 23. Analog Input Equivalent Circuit
Since the AD7400 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. The amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD7400. When a capacitive load is switched onto the output of an op amp, the amplitude momentarily drops. The op amp tries to correct the situation and, in the process, hits its slew rate limit. This nonlinear response, which can cause excessive ringing, can lead to distortion. To remedy the situation, a low-pass RC filter can be connected between the amplifier and the input to the AD7400. The external capacitor at each input aids in supplying the current spikes created during the sampling process, and the resistor isolates the op amp from the transient nature of the load. The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 24. A capacitor between the two input pins sources or sinks charge to allow most of the charge that is needed by one input to be effectively supplied by the other input. The series resistor again isolates any op amp from the current spikes created during the sampling process. Recommended values for the resistors and capacitor are 22 and 47 pF, respectively.
VIN+ R C VIN- R
AD7400
04718-028
Figure 24. Differential Input RC Network
04718-027
Rev. A | Page 14 of 20
AD7400
/*Perform the Sinc ACTION*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 0; to a -1 for 2's comp */ else ip_data1 <= 1; Z = one sample delay WORD_CLK = output word rate */ always @ (posedge word_clk or posedge reset) if(reset) begin acc3_d2 <= 0; diff1_d <= 0; diff2_d <= 0; diff1 <= 0; diff2 <= 0; diff3 <= 0; end else begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end /* Clock the Sinc output into an output register
WORD_CLK
04718-023
/* change from a 0
/*ACCUMULATOR (INTEGRATOR) Perform the accumulation (IIR) at the speed of the modulator.
MCLKOUT ACC1+ IP_DATA1 + Z + Z + ACC2+ Z ACC3
04718-021
Figure 25. Accumulator
Z = one sample delay MCLKOUT = modulators conversion bit rate */ always @ (negedge mclk1 or posedge reset) if (reset) begin /*initialize acc registers on reset*/ acc1 <= 0; acc2 <= 0; acc3 <= 0; end else begin /*perform accumulation process*/ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end /*DECIMATION STAGE (MCLKOUT/ WORD_CLK) */ always @ (posedge mclk1 or posedge reset) if (reset) word_count <= 0; else word_count <= word_count + 1; always @ (word_count) word_clk <= word_count[7]; /*DIFFERENTIATOR ( including decimation stage) Perform the differentiation stage (FIR) at a lower speed.
ACC3 Z-1 WORD_CLK + - Z-1 DIFF1 + - Z-1
04718-022
DIFF3
DATA
Figure 27. Clocking Sinc Output into an Output Register
WORD_CLK = output word rate */ always @ (posedge word_clk) begin DATA[15] DATA[14] DATA[13] DATA[12] DATA[11] DATA[10] DATA[9] DATA[8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] end endmodule <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= diff3[23]; diff3[22]; diff3[21]; diff3[20]; diff3[19]; diff3[18]; diff3[17]; diff3[16]; diff3[15]; diff3[14]; diff3[13]; diff3[12]; diff3[11]; diff3[10]; diff3[9]; diff3[8];
DIFF2
+ -
DIFF3
Figure 26. Differentiator
Rev. A | Page 15 of 20
AD7400
90 80 70 60
SNR (dB)
SINC3
SINC2
50 40 30 20
04718-025
SINC1
10 0
1
10
100 DECIMATION RATE
1k
Figure 28. SNR vs. Decimation Rate for Different Filter Types
Rev. A | Page 16 of 20
AD7400 APPLICATION INFORMATION
GROUNDING AND LAYOUT
Supply decoupling with a value of 100 nF is strongly recommended on both VDD1 and VDD2. Decoupling on one or both VDD1 pins does not significantly affect performance. In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed so that any coupling that occurs equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Any decoupling used should be placed as close to the supply pins as possible. Series resistance in the analog inputs should be minimized to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. Beware of mismatch and thermocouple effects on the analog input PCB tracks to reduce offset drift. These tests subjected populations of devices to continuous cross-isolation voltages. To accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. The time to failure values of these units were recorded and used to calculate acceleration factors. These factors were then used to calculate the time to failure under normal operating conditions. The values shown in Table 7 are the lesser of the following two values: * * The value that ensures at least a 50-year lifetime of continuous use. The maximum CSA/VDE approved working voltage.
It should also be noted that the lifetime of the AD7400 varies according to the waveform type imposed across the isolation barrier. The iCoupler insulation structure is stressed differently depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 29, Figure 30, and Figure 31 illustrate the different isolation voltage waveforms.
RATED PEAK VOLTAGE
04718-029
EVALUATING THE AD7400 PERFORMANCE
A simple standalone AD7400 evaluation board is available with split ground planes and a board split beneath the AD7400 package to ensure isolation. This board allows access to each pin on the device for evaluation purposes. External supplies and all other circuitry (such as a digital filter) must be provided by the user.
0V
Figure 29. Bipolar AC Waveform
RATED PEAK VOLTAGE
04718-030
INSULATION LIFETIME
All insulation structures, subjected to sufficient time and/or voltage, are vulnerable to breakdown. In addition to the testing performed by the regulatory agencies, Analog Devices has carried out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7400.
0V
Figure 30. Unipolar AC Waveform
RATED PEAK VOLTAGE
04718-031
0V
Figure 31. DC Waveform
Rev. A | Page 17 of 20
AD7400 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model AD7400YRWZ 1 AD7400YRWZ-REEL1 AD7400YRWZ-REEL71 EVAL-AD7400EB
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C
Package Description 16-Lead Standard Small Outline Package (SOIC_W) 16-Lead Standard Small Outline Package (SOIC_W) 16-Lead Standard Small Outline Package (SOIC_W) Standalone Evaluation Board
112906-B
Package Option RW-16 RW-16 RW-16
Z = Pb-free part.
Rev. A | Page 18 of 20
AD7400 NOTES
Rev. A | Page 19 of 20
AD7400 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04718-0-12/06(A)
Rev. A | Page 20 of 20

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